General Procedure for Configuring DMA
2-2 ADSP-21368 SHARC Processor Hardware Reference
To further increase off-chip I/O, multiple DMAs can occur at the same
time. The IOP accomplishes this by managing DMAs of processor mem-
ory through the TWI, UART, SPI, input data port (IDP), and serial ports.
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Accesses to IOP spaces (from the processor core) should not use
Type 1 (dual access) or LW instructions.
General Procedure for Configuring DMA
To configure the ADSP-21367/8/9 and ADSP-2137x processors to use
DMA, use the following general procedure.
1. Determine which DMA options you want to use:
• IOP/core interaction method – interrupt-driven or sta-
tus-driven (polling)
• DMA transfer method – chained, non-chained, or delay line
• Channel priority scheme – fixed or rotating
2. Determine how you want the DMA to operate:
• Set up the data’s source and/or destination addresses
(INDEX)
• Set up the word COUNT (data buffer size)
• Configure the MODIFY values (step size)
3. Configure the peripheral(s):
• External port (includes AMI, SDRAM)
• Serial ports (SPORTs)
• Universal asynchronous receive/transmit (UART)
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