Moving Data Between SPORTs and Internal Memory
5-76 ADSP-21368 SHARC Processor Hardware Reference
Load the
II, IM, and C registers with a starting address for the buffer, an
address modifier, and a word count, respectively. These registers can be
written from the core processor.
Once SPORT DMA is enabled, the processor’s DMA controller automat-
ically transfers received data words in the receive buffer to the buffer in
internal memory. Likewise, when the SPORT is ready to transmit data,
the DMA controller automatically transfers a word from internal memory
to the transmit buffer. The controller continues these transfers until the
entire data buffer is received or transmitted.
When the count register of an active DMA channel reaches zero, the
SPORT generates the corresponding interrupt.
SPORT DMA Parameter Registers
A DMA channel consists of a set of parameter registers that implements a
data buffer in internal memory and the hardware the SPORT uses to
request DMA service. The parameter registers for each SPORT DMA
channel and their addresses are shown in Table 5-13. These registers are
part of the processor’s memory-mapped IOP register set.
Table 5-12. SPORT DMA Parameter Registers
Register
(Y = A or B, and
x = 0 – 5)
Width Description
IISPxy 19 bits DMA channel; x index; start address for data buffer
IMSPxy 16 bits DMA channel; x modify; address increment
CSPxy 16 bits DMA channel; x count; number of words to transmit
CPSPxy 20 bits DMA channel; x chain pointer; address containing the
next set of data buffer parameters
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