Frame Sync Options
5-42 ADSP-21368 SHARC Processor Hardware Reference
mode of operation allows data to be transmitted only at specific times.
When
DIFS = 0 and SPTRAN = 0, a receive SPORTx_FS signal is generated
only when receive data buffer status is not full.
When DIFS = 1 and SPTRAN = 1, the internally-generated transmit frame
sync is output at its programmed interval regardless of whether new data is
available in the transmit buffer. The processor generates the transmit
SPORTx_FS signal at the frequency specified by the value loaded in the DIVx
registers. If a frame sync occurs when the transmitter FIFO is empty, the
MSB or LSB (depending on how the LSBF bit in SPCTL is set) of the previ-
ous word is transmitted. When DIFS = 1 and SPTRAN = 0, a receive
SPORTx_FS signal is generated regardless of the receive data buffer status.
Depending on the SPORT operating mode, the transmitter underflow
(TUVF_A or TUVF_B) bit is set if the transmit buffer does not have new data
when a frame sync occurs; or a receive overflow bit (ROVF_A or ROVF_B) is
set if the receive buffers are full and a new data word is received.
If the internally-generated frame sync is used and DIFS=0, a single write to
the transmit data register is required to start the transfer.
Frame Sync Error Detection
Similar to the SPORTs on previous SHARC processors, the SPORTs can
detect underflow and overflow errors. In addition to this, the SPORTs on
the ADSP-21367/8/9 and ADSP-2137x processors can also detect frame
syncs that are occurring early, even before the last transmit or receive
completes.
To detect these errors, these processors have a new error interrupt that
works for all eight SPORTs together. It is triggered on a data underflow,
data overflow, or frame sync error in their respective channels.
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