PWM Registers
8-20 ADSP-21368 SHARC Processor Hardware Reference
• The two’s-complement integer value in the
PWMAx registers controls
the duty cycle of the signals on the pwm_ah and pwm_al pins.
• The two’s-complement integer value in the PWMBx registers control
the duty cycle of the signals on pwm_bh and pwm_bl pins.
The duty cycle registers are programmed in two’s-complement integer
counts of the fundamental time unit, tPCLK, and define the desired
on-time of the high side PWM signal produced by the three-phase timing
unit over half the PWM period. The duty cycle register range is from
(–PWMPERIOD ÷ 2 – PWMDT) to (+PWMPERIOD ÷ 2 + PWMDT)
which, by definition, is scaled such that a value of 0 represents a 50%
PWM duty cycle. The switching signals produced by the three-phase tim-
ing unit are also adjusted to incorporate the programmed dead time value
in the PWMDT register. The three-phase timing unit produces active low sig-
nals so that a low level corresponds to a command to turn on the
associated power device.
Output Enable
The PWMSEG register contains six bits (0 to 5) that can be used to individu-
ally enable or disable each of the six PWM outputs. If the associated bit of
the
PWMSEG register is set (=1), then the corresponding PWM output is dis-
abled, regardless of the value of the corresponding duty cycle register. This
PWM output signal remains disabled as long as the corresponding
enable/disable bit of the PWMSEGx register is set. Programs should imple-
ment this function after the crossover function. After reset, all six enable
bits of the
PWMSEG register are cleared so that all PWM outputs are enabled
(default). In the same manner as the duty cycle registers, the
PWMSEG regis-
ter is latched on the rising edge of the pwm_pwmsync_out signal. Therefore,
in single-update mode, changes to this register only become effective at
the start of each PWM cycle. In double-update mode, the PWMSEG register
can also be updated at the midpoint of the PWM cycle.
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