Peripheral Interrupt Priority Control Registers
A-164 ADSP-21368 SHARC Processor Hardware Reference
Peripheral Interrupt Priority Control
Registers
The following sections provide descriptions of the programmable inter-
rupts that are used in the ADSP-21367/8/9 and ADSP-2137x processors.
For information on the interrupt registers and the interrupt vector table,
see Appendix B, Interrupts.
Peripheral Interrupt Priority Control
Registers (PICRx)
These registers allow programs to substitute the default interrupts for
some other interrupt source. Table A-69 lists the locations to program
into the IOP programmable interrupt control registers (PICR) to route an
IOP interrupt source to a corresponding processor interrupt location.
Table A-69 defines the PICR bits which are programmed to select the
source for each peripheral interrupt. Priority programming can be accom-
plished by changing the sources for each peripheral interrupt. For
example, if peripheral x needs high priority, the high priority peripheral
interrupt source is set as that peripheral.
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