ADSP-21368 SHARC Processor Hardware Reference A-165
Register Reference
Table A-69. Peripheral Interrupt Controller Routing Table
Interrupt
Name
Vector
Address
Programmable
Interrupt Control
Register (PICR)
Default
Select
Value
Default Function Priority
P0I 0x2C PICR0[4:0] 0x00 DAI1I interrupt HIGHEST
P1I 0x30 PICR0[9:5] 0x01 SPIA interrupt
P2I 0x34 PICR0[14:10] 0x02 IOP GP timer-0 interrupt
P3I 0x38 PICR0[19:15] 0x03 SPORT1 interrupt
P4I 0x3C PICR0[24:20] 0x04 SPORT3 interrupt
P5I 0x40 PICR0[29:25] 0x05 SPORT5 interrupt
P6I 0x44 PICR1[4:0] 0x06 SPORT0 interrupt
P7I 0X48 PICR1[9:5] 0x07 SPORT2 interrupt
P8I 0X4C PICR1[14:10] 0x08 SPORT4 interrupt
P9I 0X50 PICR1[19 :15] 0x09 External port DMA
channel0 interrupt
P10I 0X54 PICR1[24:20] 0x0A IOP GP timer-1 interrupt
P11I 0x58 PICR1[29:25] 0x0B SPORT7 interrupt
P12I 0x5C PICR2[4:0] 0x0C DAI2I interrupt
P13I 0x60 PICR2[9:5] 0x0D External port DMA
channel1 interrupt
P14I 0x64 PICR2[14:10] 0x0E DPI interrupt
P15I 0x68 PICR2[19:15] 0x0F MEM/MEM interrupt
P16I 0x6C PICR2[24:20] 0x10 SPORT6 interrupt
P17I 0x70 PICR2[29:25] 0x11 IOP GP timer-2 interrupt
P18I 0x74 PICR3[4:0] 0x12 SPIB interrupt
UART0RxI 0x13 UART 0 receive interrupt
UART1RxI 0x14 UART 1 receive interrupt
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