FIFO to Memory Data Transfer
7-22 ADSP-21368 SHARC Processor Hardware Reference
6. Enable DMA, IDP, and PDAP (if required) by setting each of the
following bits = 1:
•
IDP_DMA_EN bit (bit 5 of the IDP_CTL0 register)
• IDP_DMA_ENx bits in IDP_CTL1 register to enable the DMA of
the selected channel
• IDP_PDAP_EN bit (bit 31 in IDP_PP_CTL register)
• IDP_ENx of IDP_CTL1 to enable the selected channel
• IDP_ENABLE bit (bit 7 in the IDP_CTL0 register)
A DAI interrupt is generated at the end of each DMA.
7. After the DMA completes, connect the clock and frame sync sig-
nals to 0.
Ping-Pong DMA
This mode gets activated when the IDP_DMA_EN bit of the IDP_CTL0 register
and the IDP_PINGx bit in the IDP_CTL1 register are set for a particular
channel.
In ping-pong DMA, the parameters have two memory index values (index
A and index B), one count value and one modifier value. The DMA starts
the transfer with the memory indexed by A. When the transfer is com-
pleted as per the value in the count register, the DMA restarts with the
memory location indexed by B. The DMA restarts with index A after the
transfer to memory with index B is completed as per the count value. This
repeats until the DMA is stopped by resetting the IDP_DMA_EN or
IDP_PINGx bits.
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