ADSP-21368 SHARC Processor Hardware Reference 2-47
I/O Processor
Notes On Using DMA With the UART
The following should be noted when performing DMA in conjunction
with the UART module.
1. DMA can be interrupted by resetting the DEN bit, but none of the
other control settings should be changed. If the UART is enabled
again, then interrupted DMA can be resumed by resetting the DEN
bit.
2. Disabling the UART by resetting the enable (EN) bit flushes data in
the transmit/receive buffer. Resetting the UART during a DMA
operation is prohibited and leads to data loss.
3. Do not disable chaining (CHEN bit in the control registers) when a
chaining DMA is in progress. If this occurs, a DMA completion
interrupt will not be generated when the PCI bit = 1.
4. During a receive DMA, a read of the receiver buffer (UARTxRBR) is
not allowed. If needed, programs should read the receiver shadow
buffer (UARTxRBRSH).
5. During DMA, the UARTDR bit in the UARTxLSR register is cleared
automatically.
6. DMA may be used in 9-bit mode, once the address has been
detected. If, between DMAs, another address is received, an
address detect interrupt is generated (if enabled). At this point, the
UARTxRBRSH shadow register can be read to find the 9-bit word (the
address). The
UARTxLSR register also shows the UARTRX9D (address
detect) bit.
To Next Page
Loading...
Need help?
General
