ADSP-21368 SHARC Processor Hardware Reference 5-11
Serial Ports
The operating mode (
OPMODE) bit of the SPCTLx register selects between I
2
S
mode/left-justified sample pair mode, and non-I
2
S mode (DSP serial
port/multichannel mode). In multichannel mode, the MCEA bit in the SPM-
CTLx
register enables the A channels and the MCEB bit in the
SPMCTLx register enables the B channels. The data direction bit (SPTRAN)
selects whether the port is a transmitter or receiver in all the SPORT oper-
ation modes.
If the SPTRAN bit is set (= 1), the SPORT becomes a transmitter and all the
other control bits are defined accordingly. Similarly, when SPTRAN = 0, the
SPORT becomes a receiver.
L
Companding logic is only supported for multi-channel mode and
packed I
2
S mode. Companding logic is available only for SPORT0,
2, 4 and 6 A channels. Expansion logic is now available only in
SPORT1, 3, 5 and 7 A channels.
The SPCTLx register is unique in that the name and functionality of its bits
changes depending on the operation mode selected. In each section that
follows, the bit names associated with the operating modes are described.
Table 5-1 provides values for each of the bits in the SPORT control
(SPCTLx) registers that must be set in order to configure each specific
SPORT operation mode. An X in a field indicates that the bit is not sup-
ported for the specified operating mode.
Table 5-1. SPORT Operation Modes
Operating Modes
Bits
OPMODE LAFS FRFS MCEA MCEB SLENx
Standard DSP Serial Mode 0 0, 1 X 0 0 3-32
1
I
2
S (Tx/Rx on Left Channel
First)
1 0 1 0 0 8-32
I
2
S (Tx/Rx on Right Channel
First)
1 0 0 0 0 8-32
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