ADSP-21368 SHARC Processor Hardware Reference 11-1
11 UART PORT CONTROLLER
The universal asynchronous receiver/transmitter (UART) is a full-duplex
peripheral compatible with the PC-style, industry-standard UART. The
UART converts data between serial and parallel formats. The serial format
follows an asynchronous protocol that supports various word lengths, stop
bits, and parity generation options. The UART includes interrupt han-
dling hardware. Interrupts can be generated from 12 different events.
The ADSP-21367/8/9 and ADSP-2137x processors contain two UARTs
which support multiprocessor communication using 9-bit address detec-
tion. This allows the units to be used in multi-drop networks using the
RS-485 data interface standard.
The two independent UARTs are referred to as UART0 and UART1.
Both are identical and each has its own set of control and status registers.
The content in this chapter applies to both UARTs unless otherwise
specified.
The UART is a DMA-capable peripheral with support for separate trans-
mit and receive DMA master channels. It can be used in either DMA or
programmed non-DMA modes of operation. The non-DMA mode
requires software management of the data flow using either interrupts or
polling. The DMA method requires minimal software intervention as the
DMA engine itself moves the data. For more information, see “UART
DMA” on page 2-44.
Either one of the peripheral timers can be used to provide a hard-
ware-assisted autobaud detection mechanism for use with the UART. See
the ADSP-2136x SHARC Processor Programming Reference, “Timers” chap-
ter for more information.
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