Programming Examples
12-18 ADSP-21368 SHARC Processor Hardware Reference
5. Program the
TWIMCTL register. This prepares and enables master
mode operation. As an example, programming the value 0x0201
enables master mode operation, generates a 7-bit address, sets the
direction to master-transmit, uses standard mode timing, and
transmits 8 data bytes before generating a stop condition.
Table 12-3 shows what the interaction between the TWI controller and
the processor might look like using this example.
Master Mode Receive
Follow these programming steps for a single master mode transmit:
1. Program the TWIMADDR register. This defines the address transmit-
ted during the address phase of the transfer.
2. Program the
TWIFIFOCTL register. Indicate if receive FIFO buffer
interrupts should occur with each byte received (8 bits) or with
each 2 bytes received (16 bits).
3. Program the TWIIMASK register. Enable bits associated with the
desired interrupt sources. For example, programming the value
0x0030 results in an interrupt output to the processor in the event
that the master transfer completes, and the master transfer has an
error.
Table 12-3. Master Mode Transmit Setup Interaction
TWI Controller Master Processor
Interrupt: TWITXINT – Transmit buffer has 1 or
2 bytes empty (according to XMTINTLEN).
Write transmit FIFO buffer.
Acknowledge: Clear interrupt source bits.
... ...
Interrupt: TWIMCOMP – Master transfer com-
plete.
Acknowledge: Clear interrupt source bits.
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