ADSP-21368 SHARC Processor Hardware Reference A-127
Register Reference
UART DMA Registers
The UART supports full-duplex DMA. Separate receive and transmit
DMA channels are responsible for moving data between the peripheral
and memory in this mode. The UART uses eight registers to control and
provide status on DMA. The following sections provide descriptions of
these registers.
Table A-48. UART Mode Register Bit Descriptions
Bit Name Description
0UARTPACKPacking Enable.
0 = No pack
1 = Packing enabled. Consecutive data words (example 0xAB
and 0xCD) are packed as 0x00CD 00AB in the receiver, and
0x00CD 00AB is transmitted as two words of 0xAB and
0xCD successively from the transmitter. For more informa-
tion, see “Packing Mode” on page 11-15.
1UARTPKSYNSynchronize Data Packing in RX. When written with a 1,
the next data byte goes to the lower byte position of the RBR
register. This is a write-only bit and always returns zero on
reads.
2UARTTX9Enable 9-Bit Tx in Transmitter.
0 = I/O mode
1 = 9-bit transmission in transmitter
3UARTRX9Enable 9-Bit Tx in Receiver.
0 = I/O mode
1 = 9-bit transmission in receiver
4UARTAENEnable Address Detect (If RX9 = 1).
0 = Disable address detection; all bytes are received
1 = Enable address detection; interrupt and load of RBR
when RX9D is set
6–5 UARTPST1,
UARTPST0
Pin Status.
11 = UART output is high in disabled state (default)
00 = UART output is low in disabled state
01/10 = UART output is three-stated in the disabled state
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