ADSP-21368 SHARC Processor Hardware Reference A-59
Register Reference
SPI Receive Buffer Registers (RXSPI, RXSPIB)
These registers’ addresses are 0x1004 (for RXSPI) and 0x2804 (for RXSPIB).
The reset values are undefined. These are 32-bit, read-only registers acces-
sible by the core or DMA controller. At the end of a data transfer, RXSPIx
is loaded with the data in the shift register. During a DMA receive opera-
tion, the data in RXSPIx is automatically loaded into the internal memory.
For core- or interrupt-driven transfers, you can also use the RXS status bits
in the SPISTAT register to determine if the receive buffer is full.
RXSPI Shadow Registers
(RXSPI_SHADOW, RXSPIB_SHADOW)
These registers’ addresses are 0x1006 (for RXSPI_SHADOW) and 0x2806 (for
RXSPIB_SHADOW). The reset values are undefined. These registers act as
shadow registers for the receive data buffer, RXSPI and RXSPIB registers,
and are used to aid software debugging. These registers, are at a different
address from RXSPI and RXSPIB but their contents are identical to that of
RXSPI and RXSPIB. When a software read of RXSPIx occurs, the RXS bit is
cleared and an SPI transfer may be initiated (if TIMOD=00). No such hard-
ware action occurs when the shadow register is read.
SPI Transmit Buffer Registers (TXSPI, TXSPIB)
These registers’ addresses are 0x1003 (for TXSPI) and 0x2803 (for TXSPIB).
The reset values are undefined. These SPI transmit data registers are
32-bit registers that are part of the IOP register set and can be accessed by
the core or the DMA controller. Data is loaded into these registers before
being transmitted. Prior to the beginning of a data transfer, data in
TXSPIx
is automatically loaded into the transmit shift register. During a DMA
transmit operation, the data in
TXSPIx is automatically loaded from inter-
nal memory.
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