ADSP-21368 SHARC Processor Hardware Reference 11-11
UART Port Controller
If software stops transmission, it must read the
UARTxIIR register to reset
the interrupt request. As long as the UARTxIIR register reads 0x04 or 0x06
(indicating that another interrupt of higher priority is pending), the UAR-
TxTHR
empty latch cannot be cleared by reading the UARTxIIR register.
L
The following restrictions should be noted.
1. If either the line status interrupt or the receive data interrupt has
been assigned a lower interrupt priority by the interrupt controller,
a deadlock condition can occur. To avoid this, always assign the
lowest priority of the enabled UART interrupts to the UARTxTHR
empty event.
2. Because of the destructive nature of reading these registers, shadow
registers are provided for reading the contents of the corresponding
main registers. The shadow registers, UARTxIIRSH, return exactly
the same contents as the main register, but without changing the
status in any way. These registers are 32-bit registers located at
address 0x3C09 (for UART0IIRSH) and 0x4009 (for UART1IIRSH).
UARTxDLL and UARTxDLH Registers
The bit rate is characterized by the peripheral clock (PCLK = 2 x CCLK) and
the 16-bit divisor. The divisor is split into the UART divisor latch low
byte register (
UARTxDLL) and the UART divisor latch high byte register
(UARTxDLH). These registers form a 16-bit divisor. The baud clock is
divided by 16 so that:
Divisor = 1 when
UARTxDLL = UARTxDLH = 1
Divisor = 65,535 when
UARTxDLL = UARTxDLH = FF
The UARTxDLL register is mapped to the same address as the UARTxTHR and
UARTxRBR registers. The UARTxDLH register is mapped to the same address as
the interrupt enable register (
UARTxIER). The DLAB bit in the UARTxLCR reg-
ister must be set before the UART divisor latch registers can be accessed.
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