UART Control and Status Registers
11-10 ADSP-21368 SHARC Processor Hardware Reference
interrupt priority using the peripheral interrupt priority control registers.
For more information, see “Peripheral Interrupt Priority Control Regis-
ters” on page A-164.
When cleared, the pending interrupt bit (
NINT) signals that an interrupt is
pending. The STATUS field indicates the highest priority pending inter-
rupt. The receive line status has the highest priority; the UARTTXFI
interrupt has the lowest priority. In the case where both interrupts are sig-
nalling, the UARTxIIR register reads 0x06.
When a UART interrupt is pending, the interrupt service routine (ISR)
needs to clear the interrupt latch explicitly. For information on how to
clear the latches see “Interrupt Identification Registers (UARTxIIR)” on
page A-124.
The transmit interrupt request is cleared by writing new data to the
UAR-
TxTHR
register or by reading the UARTxIIR register. Please note the special
role of the
UARTxIIR register read in the case where the service routine does
not want to transmit further data.
Table 11-1. IIR Register in I/O Mode
Bit Status NINT Interrupt
Priority
Interrupt Type Cleared When...
000 1 – No interrupt –
011 0 1 Rx line status LSR is read
100 0 2 Address detect RBR is read
010 0 3 Rx data ready RBR is read
001 0 4 THR empty Write THR or Read
IIR when priority = 4
000 0 5 THR and TSR empty Write THR or Read
IIR when priority = 5
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