ADSP-21368 SHARC Processor Hardware Reference 3-27
External Port
controller or through direct core writes. Writes to the AMI set a status bit
(
AMITXS, bit 2 in the AMISTAT register) and initiate the external write
access.
Once a full word is transferred out of the AMI, the AMITXS bit is cleared
and new writes are allowed. No more external transfers can start while the
AMI module is empty.
Whenever the AMITX is empty, the DMA controller or a direct access from
the processor core can write fresh data into the AMI. If the register is full,
further writes from the core (or DMA controller) are stalled.
Data Packing
Data unpacking for memory writes uses the packing disable bit (PKDIS, bit
3) and the most significant word first (MSWF, bit 4) bits in the AMICTLx
register.
For packed data mode where PKDIS = 0 MSWF = 0, the order of unpacking
for 32- to 8-bit data is: the first byte is bits 7–0, the second byte is bits
15–8, and so on.
For packed data mode where PKDIS = 0 MSWF = 1, the unpacking order for
32- to 8-bit data is: first byte received is bits 31–24, the second byte is bits
23–16, and so on.
If
PKDIS bit is set (=1), only the 16- or 8-bit least significant portion of the
32-bit data is written to external memory.
Both of these methods apply to 32- to 16-bit unpacking as well. These
modes are summarized in Table 3-10.
L
For direct access (core and DMA), the received data is also
unpacked, depending on the setting of the
PKDIS bit. The order of
unpacking is dependent on the
MSWF bit in AMICTLx registers.
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