SDRAM Controller
3-58 ADSP-21368 SHARC Processor Hardware Reference
SDRAM Controller Address Mapping
To access SDRAM, the SDC multiplexes the internal 32-bit, non-multi-
plexed address into a row and column address. The row and column
address mappings for 32-bit and 16-bit addresses are shown in
Table 3-25. The row and column addresses are muxed to pins
A14–A0 of the processor. The SDRAM address pin A10 is connected to the
processor’s SDA10 pin. The SDC bank address pins BA[0] and BA[1], are
connected to the processor’s A[17] and A[18] pins.
L
For 2 banked SDRAMs connect BA with A[17].
SDC Operation
The AMI normally generates an external memory address, which then
asserts the corresponding CS select on the SDRAM, along with RD and WR
strobes. However these control signals are not used by the SDRAM con-
troller. The internal strobes are used to generate pulsed commands (MSx,
SDCKE, SDRAS, SDCAS, SDWE) within a truth table Table 3-26. The memory
access to SDRAM is based by mapping ADDR[27:0] causing an internal
memory select to SDRAM space.
The configuration is programmed in the SDCTL register. The SDRAM con-
troller can hold off the processor core or DMA controller with an
internally connected acknowledge signal, as controlled by refresh, or page
miss latency overhead.
A programmable refresh counter is provided which generates background
auto-refresh cycles at the required refresh rate based on the clock fre-
quency used. The refresh counter period is specified with the
SDRRC field
in the SDRAM refresh rate control register (“SPERRCTLx Register” on
page A-48).
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