ADSP-21368 SHARC Processor Hardware Reference 5-19
Serial Ports
Enabling SPORT DMA (SDEN)
DMA can be enabled or disabled independently on any SPORT transmit
and receive channels. For more information, see “Moving Data Between
SPORTs and Internal Memory” on page 5-73. Set
SDEN_A or SDEN_B (=1)
to enable DMA and set the channel in DMA-driven data transfer mode.
Clear SDEN_A or SDEN_B (=0) to disable DMA and set the channel in an
interrupt-driven data transfer mode.
Interrupt-Driven Data Transfer Mode
Both the A and B channels share a common interrupt vector, regardless of
whether they are configured as transmitters or receivers.
The SPORT generates an interrupt in every peripheral clock cycle when
the transmit buffer has a vacancy or the receive buffer has data. To deter-
mine the source of an interrupt, applications must check the transmit or
receive data buffer status bits. For details, see “Single Word Transfers” on
page 5-81.
DMA-Driven Data Transfer Mode
Each transmitter and receiver has its own DMA registers. For details, see
“Selecting Transmit and Receive Channel Order (FRFS)” on page 5-18
and “Moving Data Between SPORTs and Internal Memory” on
page 5-73. The same DMA channel drives both channels in the pair for
the transmitter or receiver. The software application must stop multiplex-
ing the left and right channel data received by the receive buffer, as the left
and right data is interleaved in the DMA buffers.
Channel A and B on each SPORT share a common interrupt vector. The
DMA controller generates an interrupt at the end of DMA transfer only.
Figure 5-3 shows the relationship between frame sync (word select), serial
clock, and left-justified sample pair mode data. Timing for word select is
the same as for frame sync.
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