External Memory Interface
3-18 ADSP-21368 SHARC Processor Hardware Reference
External Port Arbitration Logic
The external port arbitration logic controls the arbitration between the
two DMA channels and processor core. The following control the arbitra-
tion logic.
• The
EPCTL register can be programmed to use the various features
of arbitration between different channels. DMA channels 0 and 1
can be programmed for rotating or fixed priority.
• The winning DMA channel can be arbitrated with the core chan-
nel. The EBPR and DMAPR bits define the priorities.
Channel Freezing
The external port is idle when DMA engines are idle and no core access is
pending. When multiple DMA channels are reading data from SDRAM
memory, channel freezing can improve the data throughput. By setting the
freeze bits (FRZDMA, bits 10–9 and FRZCR, bits 14–13), each channel is fro-
zen for programmed accesses. For example, if the processor core is frozen
for 16 accesses, and if the core requests 16 accesses to SDRAM sequen-
tially, data throughput improves. Freezing is based on the fact that
sequential accesses to the SDRAM provide better throughput then
non-sequential accesses. Freezing does not add value for write accesses.
For details on throughput, see “SDRAM Timing” on page 3-74.
Managing Data Paths
The
DATE bits (bits 18–15) are used to enable the data paths in the input
path. If the
DATE bits are set (=1), then the incoming data that corresponds
to the set bits are connected to zero. This helps to avoid the floating pin
data coming in to the processor.
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