ADSP-21368 SHARC Processor Hardware Reference 11-3
UART Port Controller
UART Control and Status Registers
The processor provides a set of PC-style, industry-standard control and
status registers for each UART. These memory-mapped registers (MMRs)
are byte-wide registers that are mapped as half-words with the most signif-
icant byte zero-filled.
Consistent with industry-standard interfaces, multiple registers are
mapped to the same address location. The transmit holding, divisor latch
low, and receive buffer registers share an address and the interrupt enable
and divisor latch high registers share an address. The divisor latch access
bit (UARTDLAB, bit 7) in the line control register (UARTxLCR) controls which
set of registers is accessible at a given time.
Transmit and receive channels are both buffered. The UARTxTHR register
buffers the transmit shift register (UARTxTSR) and the UARTxRBR register
buffers the receive shift register (UARTxRSR). The shift registers are not
directly accessible by software.
These registers are also shown and described in “UART Control and Sta-
tus Registers” on page A-118.
UARTxLCR Registers
The UART line control register (UARTxLCR) controls the format of received
and transmitted character frames. The UARTSB bit (bit 6) functions even
when the UART clock is disabled. Since the transmit pin normally drives
high, it can be used as a flag output pin when the UART is not used. The
parity and word length select controls are not valid in 9-bit mode. In 9-bit
mode, the word length is always 8 and the 9th bit is transmitted instead of
the parity bit.
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