Processor Pin Descriptions
14-12 ADSP-21368 SHARC Processor Hardware Reference
And for
FLAGS4–15:
• In output mode, if the same flag is mapped to both data pins and
DPI pins, then the output comes from both pins.
• In input mode, if the same flag is mapped to both data pins and
DPI pins, the input from data pins is given priority.
• In input mode, if the same flag is mapped to both upper and lower
data pins, the input from the lower data pins is given priority.
RESETOUT/CLKOUT/RUNRSTIN
The default behavior of the RESETOUT pin is to provide a 4096 cycle delay
that allows the PLL to lock. In PLL bypass mode, where the CLK_CFG pins
= 11, this pin functions as a CLKOUT signal to clock synchronous peripher-
als and memory. This can also be accomplished by setting (= 1) bit 12
(CLKOUTEN) in the power management control register and this functional-
ity applies to all ADSP-21367/8/9 and ADSP-2137x processors. Finally,
on the ADSP-2137x processors only, the RESETOUT pin can configured to
provide a running reset. For more information, see “Running Reset
(ADSP-2137x)” on page 14-22.
JTAG Interface Pins
The JTAG test access port (TAP) consists of the TCK, TMS, TDI, TDO, and
TRST pins. The JTAG port can be connected to a controller that performs
a boundary scan for testing purposes. This port is also used by the Analog
Devices DSP Tools product line of JTAG emulators and development
software to access on-chip emulation features. To allow the use of the
emulator, a connector for its in-circuit probe must be included in the tar-
get system.
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