ADSP-21368 SHARC Processor Hardware Reference 11-15
UART Port Controller
Packing Mode
The UART provides packed and unpacked modes of data transfer to and
from the internal memory of the ADSP-21367/8/9 and ADSP-2137x pro-
cessors. This mode is set using the UARTPACK bit (bit 0) in the UARTxMODE
register. In unpacked mode, the data word is appended to the left with 24
zeros during transmission or reception. In packed mode, two words of
data are transmitted or received with their corresponding higher bytes
filled with zeros. For example, consecutive data words 0xAB and 0xCD
are packed as 0x00CD 00AB in the receiver, and 0x00CD 00AB is trans-
mitted as two words of 0xAB and 0xCD successively from the transmitter.
The packed feature is provided to use the internal memory of the proces-
sor in a more efficient manner. Packing is available in both I/O and DMA
modes. A control bit, UARTPKSYN, can be used to re synchronize the pack-
ing. For information on using the UART for DMA transfers, see “UART
DMA” on page 2-44.
Note that in packed mode, both the transmitter and receiver operate with
an even number of words. A transmit-buffer-empty or receive-buffer-full
interrupt is generated only after an even number of words are transferred.
In 9-bit mode, the address detect interrupt can be generated whenever the
receiver gets an address word, irrespective of the packing mode. This helps
programs respond to an address word immediately. The program is
expected to take into account these features when using packed mode.
L
Programs must use care when using the packing feature in 9-bit
mode.
Programs should write the
UARTPKSYN bit (bit 1) with a 1 each time
an address is received. This starts the reception of the following
data from the lower half-word of the
UARTxRBR register.
The address-detect interrupt is generated whenever the UART
receiver receives an address, irrespective of the packing. The
DR bit
in the
UARTxLSR register can be used to discover whether the
address is in the lower (
DR = 0) or higher half-word (DR = 1).
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