ADSP-21368 SHARC Processor Hardware Reference 11-7
UART Port Controller
UARTxIER Register
The UART interrupt enable registers (UARTxIER) are used to enable
requests for system handling of empty or full states of UART data regis-
ters. Unless polling is used as a means of action, the UARTRBFIE and/or
UARTTBEIE bits in this register are normally set.
Setting these registers without enabling system DMA causes the UART to
notify the processor of the state of the data inventory by means of inter-
rupts. For proper operation in this mode, system interrupts must be
enabled, and appropriate interrupt handling routines must be present. For
backward compatibility, the UARTxIIR registers still reflect the correct
interrupt status.
With system DMA enabled, the UART uses DMA to transfer data to or
from the processor. Dedicated DMA channels are available to receive and
transmit operations. Line error handling can be configured completely
independently from the receive/transmit setup.
The UARTxIER register is mapped to the same address as the UARTxDLH reg-
ister. To access the UARTxIER register, the UARTDLAB bit in the UARTxLCR
register must be cleared.
The UART interrupts are all combined into the digital peripheral inter-
face (DPI) interrupt. The DPI_IRPTL register determines whether an
interrupt is for the transmitter or receiver. For DMA, the transmit inter-
rupt is generated when a DMA in transmit mode is complete whereas the
receive interrupt is generated when receive DMA is complete or when a
receive error occurs. The UARTxRXSTAT register reports whether the inter-
rupt is due to DMA completion or errors.
The UART receive and transmit interrupt can also be programmed
through the peripheral interrupt control registers (PICR) as separate inter-
rupts for DMA. (By default, these interrupts are not configured in the
IRPTL register—the PICR register has to be programmed to configure
them.) For I/O mode, both the transmit and receive interrupt can be
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