FIFO to Memory Data Transfer
7-28 ADSP-21368 SHARC Processor Hardware Reference
The IDP DMA parameter registers have these functions:
• Internal index registers (
IDP_DMA_Ix, IDP_DMA_AIx, IDP_DMA_BIx).
Index registers provide an internal memory address, acting as a
pointer to the next internal memory location where data is to be
written.
• Internal modify registers (IDP_DMA_Mx). Modify registers provide
the signed increment by which the DMA controller post-modifies
the corresponding internal memory index register after each DMA
write.
• Count registers (IDP_DMA_Cx, IDP_DMA_PCx). Count registers indi-
cate the number of words remaining to be transferred to internal
memory on the corresponding DMA channel.
For a descriptions of these registers see “Input Data Port DMA Control
Registers” on page A-70 and “Input Data Port Ping-Pong DMA Regis-
ters” on page A-72.
IDP (DAI) Interrupt Service Routines for DMAs
The IDP can trigger either the high priority DAI core interrupt reflected
in the DAI_IRPTL_H register or the low priority DAI core interrupt
reflected in the DAI_IRPTL_L register. The ISR must read the correspond-
ing
DAI_IRPTL_H or DAI_IRPTL_L register to find all the interrupts
currently latched. The DAI_IRPTL_H register reflects the high priority inter-
rupts and the DAI_IRPTL_L register reflects the low priority interrupts.
When these registers are read, it clears the latched interrupt bits. This is a
destructive read.
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