ADSP-21368 SHARC Processor Hardware Reference 7-29
Input Data Port
The following steps describe how an IDP ISR is handled.
1. When the DMA for a channel completes, an interrupt is generated
and program control jumps to the ISR.
2. The program clears the
IDP_DMA_EN bit in the IDP_CTL0 register
(= 0).
3. The program should read the DAI_IRPTL_L or DAI_IRPTL_H registers
to determine which DMA channels have completed. Programs may
read these register’s shadow registers (DAI_IRPTL_L_SH and
DAI_IRPTL_H_SH) without clearing the contents of the primary
registers.
To ensure that the DMA of a particular IDP channel is complete,
(all data is transferred into internal memory) wait until the
IDP_DMAx_STAT bit of that channel becomes zero in the DAI_STAT
register. This is required if a high priority DMA (for example a
SPORT DMA) is occurring at the same time as the IDP DMA.
As each DMA channel completes, a corresponding bit in either the
DAI_IRPTL_L or DAI_IRPTL_H registers for each DMA channel is set
(IDP_DMAx_INT). Refer to “DAI Interrupt Controller Registers” on
page A-112 for more information on the DAI_IRPTL_L or
DAI_IRPTL_H registers.
4. Reprogram the DMA registers for finished DMA channels.
More than one DMA channel may have completed during this
time period. For each channel, a bit is latched in the
DAI_IRPTL_L
or
DAI_IRPTL_H registers. Ensure that the DMA registers are repro-
grammed. If any of the channels are not used, then its clock and
frame sync must be held low.
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