Sample Rate Converter Architecture
10-8 ADSP-21368 SHARC Processor Hardware Reference
anti-aliasing filter, the coefficients are dynamically altered and the length
of the convolution is increased by a factor of (f
S_IN
/f
S_OUT
). This tech-
nique is supported by the Fourier transform property that if f(t) is F(ω),
then f(k × t) is F(ω/k). Thus, the range of decimation is simply limited by
the size of the RAM.
Sample Rate Converter Architecture
Figure 10-4 shows a top level block diagram of the SRC module and
Figure 10-5 shows architecture details. The sample rate converter’s FIFO
block adjusts the left and right input samples and stores them for the FIR
filter’s convolution cycle. The f
S_IN
counter provides the write address to
the FIFO block and the ramp input to the digital-servo loop. The ROM
stores the coefficients for the FIR filter convolution and performs a
high-order interpolation between the stored coefficients. The sample rate
ratio block measures the sample rate by dynamically altering the ROM
coefficients and scaling the FIR filter length and input data. The digi-
tal-servo loop automatically tracks the f
S_IN
and f
S_OUT
sample rates and
provides the RAM and ROM start addresses for the start of the FIR filter
convolution.
L
The master clock input (MCLK) shown in Figure 10-4 is peripheral
clock (PCLK) divided by 4 (which is core clock divided by 8). There-
fore,
MCLK = PCLK ÷ 4 = CCLK ÷ 8
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