ADSP-21368 SHARC Processor Hardware Reference 10-9
Asynchronous Sample Rate Converter
The FIFO receives the left and right input data and adjusts the amplitude
of the data for both the soft muting of the SRC and the scaling of the
input data by the sample rate ratio before storing the samples in RAM.
The input data is scaled by the sample rate ratio because as the FIR filter
length of the convolution increases, so does the amplitude of the convolu-
tion output. To keep the output of the FIR filter from saturating, the
input data is scaled down by multiplying it by (f
S_OUT
/f
S_IN
) when
f
S_OUT
< f
S_IN
. The FIFO also scales the input data to mute and stop
muting the SRC.
The RAM in the FIFO is 512 words deep for both left and right channels.
An offset to the write address, provided by the f
S_IN
counter, is added to
prevent the RAM read pointer from overlapping the write address. The
offset is selectable by the
GRPDLYS (group delay select) signal. A small offset
(16) is added to the write address pointer when
GRPDLYS is high, and a
large offset, (64), is added to the write address pointer when
GRPDLYS is
Figure 10-4. Sample Rate Converter Block Diagram
SERIAL
INPUT
PORT
LRCLK_I
SCLK_I
SDATA_I
SMODE_IN2-0
HARD_MUTE_IN
TDM_OUT
DE-EMPHASIS
FILTER
MUTE_OUT
DE-EMPHASIS1-0
SAMPLE
RATE
CONVERTER
MUTE_IN
SRC_RATIO14-0
SERIAL
OUTPUT
PORT
LRCLK_O
SCLK_O
SDATA_O
TDM_IN
SMODE_OUT1-0
WLENGTH_OUT1-0
21BIT_DITHER
MATCHED_PHASED_MODE
MCLK
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