ADSP-21368 SHARC Processor Hardware Reference A-109
Register Reference
DAI/DPI Registers
The registers that are described in the following sections are contained
within the digital audio and digital peripheral interfaces. The bits in these
registers are used to enable the connection of peripherals and to view sta-
tus of data transfers. For complete information on using the DAI/DPI, see
Chapter 4, Digital Audio/Digital Peripheral Interfaces.
Digital Audio Interface Status Register (DAI_STAT)
The DAI_STAT register is a read-only register and is shown in Figure A-41
and described in Table A-45. The state of all eight DMA channels is
reflected in IDP_DMAx_STAT (bits 24-17 of the DAI_STAT register). These
bits are set once the IDP_DMA_EN bit is set and remains set till the last data
of that channel is transferred (see “Input Data Port Control Register 0
(IDP_CTL0)” on page A-66). Even if the IDP_DMA_EN bit is set, it goes low
once the required number of data transfers occurs. And even when DMA
through some channel is not intended, its IDP_DMAx_STAT bit goes high.
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