ADSP-21368 SHARC Processor Hardware Reference A-49
Register Reference
SPORT Error Status Register (SPERRSTAT)
In the ADSP-21367/8/9 and ADSP-2137x processors, there is one global
interrupt status register, SPERRSTAT, that checks the status of SPORT
interrupts. This read-only register is located at address 0x2300 and is 24
bits wide (see Figure A-22).
Figure A-22. SPERRSTATx Register
SP5 DERRB Int Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Reserved
SP7 DERRB Int Status
SP4 FSERR Int Status
SP2 FSERR Int Status
SP1 FSERR Int Status
SP0 FSERR Int Status
SP7 DERRA Int Status
SP6 DERRB Int Status
SP6 DERRA Int Status
SP0 DERRA Int Status
SP0 DERRB Int Status
SP1 DERRA Int Status
SP1 DERRB Int Status
SP2 DERRA Int Status
SP2 DERRB Int Status
SP5 DERRA Int Status
SP4 DERRB Int Status
SP4 DERRA Int Status
SP3 DERRA Int Status
SP3 DERRB Int Status
SP5 FSERR Int Status
SP6 FSERR Int Status
SP7 FSERR Int Status
SP3 FSERR Int Status
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