SPORT Operation Modes
5-24 ADSP-21368 SHARC Processor Hardware Reference
When using both SPORT channels (
SPORTx_DA and SPORTx_DB) as trans-
mitters and MSTR = 1, SPTRAN = 1, and DIFS = 0, the processor generates a
frame sync signal only when both transmit buffers contain data because
both transmitters share the same SPORTx_CLK and SPORTx_FS. For continu-
ous transmission, both transmit buffers must contain new data.
When using both SPORT channels (SPORTx_DA and SPORTx_DB) as receiv-
ers and MSTR = 1, SPTRAN = 1, and DIFS = 0, the processor generates a frame
sync signal only when both receive buffers are not full because they share
the same SPORTx_CLK and SPORTxFS.
When using both SPORT channels as transmitters and MSTR = 1,
SPTRAN = 1 and DIFS = 1, the processor generates a frame sync signal at the
frequency set by FSDIVx whether or not the transmit buffers contain new
data. The DMA controller or the application is responsible for filling the
transmit buffers with data.
When using both SPORT channels as receivers and MSTR = 1, SPTRAN = 1
and DIFS = 1, the processor generates a frame sync signal at the frequency
set by FSDIV, irrespective of the receive buffer status. Bits 31–16 of the DIV
register comprise the FSDIV bit field. For more information, see “SPORT
Divisor Registers (DIVx)” on page A-44.
Enabling SPORT DMA (SDEN)
DMA can be enabled or disabled independently on any SPORTs transmit
and receive channels. For more information, see “Moving Data Between
SPORTs and Internal Memory” on page 5-73. Set
SDEN_A or SDEN_B (=1)
to enable DMA and set the channel in DMA-driven data transfer mode.
Clear
SDEN_A or SDEN_B (=0) to disable DMA and set the channel in an
interrupt-driven data transfer mode.
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