Configuring IOP/Core Interaction
2-14 ADSP-21368 SHARC Processor Hardware Reference
In general, a DMA sequence starts when one of the following occurs:
• Chaining is disabled, and the DMA enable bit transitions from low
to high.
• Chaining is enabled, DMA is enabled, and the chain pointer regis-
ter address field is written with a nonzero value. In this case, TCB
chain loading of the channel parameter registers occurs first.
• Chaining is enabled, the chain pointer register address field is non-
zero, and the current DMA sequence finishes. Again, TCB chain
loading occurs.
A DMA sequence ends when one of the following occurs:
• The count register decrements to zero, and the chain pointer regis-
ter is zero.
• Chaining is disabled and the channel’s DMA enable bit transitions
from high to low. If the DMA enable bit goes low (=0) and chain-
ing is enabled, the channel enters chain insertion mode and the
DMA sequence continues. For more information, see “Inserting a
TCB in an Active Chain” on page 2-41.
Once a program starts a DMA process, the process is influenced by two
external controls—DMA channel priority and DMA chaining. For more
information, see “Managing DMA Channel Priority” on page 2-19 or
“Chaining DMA Processes” below.
Chaining DMA Processes
The location of the DMA parameters for the next sequence comes from
the chain pointer register. In chained DMA operations, the processor
automatically initializes and then begins another DMA transfer when the
current DMA transfer is complete. In addition to the standard DMA
parameter registers, each DMA channel (SPORT, eternal port, UART and
SPI) also has a chain pointer register that points to the next set of DMA
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