Architecture
12-2 ADSP-21368 SHARC Processor Hardware Reference
• Separate multiple-byte receive and transmit FIFOs
• Low interrupt rate
• Individual override control of data and clock lines in the event of a
bus lockup
• Input filter for spike suppression
Table 12-1 shows the pins for the TWI. Two bidirectional pins externally
interface the TWI controller to the I
2
C bus. The interface is simple and
no other external connections or logic are required.
Architecture
Figure 12-1 illustrates the overall architecture of the TWI controller.
The peripheral interface supports the transfer of 32-bit wide data and is
used by the processor in the support of register and FIFO buffer reads and
writes.
The register block contains all control and status bits and reflects what can
be written or read as outlined by the programmer’s model. Status bits can
be updated by their respective functional blocks.
The FIFO buffer is configured as a 1-byte-wide, 2-deep transmit FIFO
buffer and a 1-byte-wide, 2-deep receive FIFO buffer.
Table 12-1. TWI Pins
Pin Description
SDA In/Out TWI serial data, high impedance reset value
SCL In/Out TWI serial clock, high impedance reset value
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