Features
5-2 ADSP-21368 SHARC Processor Hardware Reference
Features
Serial ports offer the following additional features and capabilities:
• Two additional SPORTs, each with their own DMA channels and
interrupts, have been added to the ADSP-21367, ADSP-21368,
ADSP-21369, and ADSP-21371 SHARC processors.
• Two bidirectional channels (A and B) per SPORT, configurable as
either transmitters or receivers. Each SPORT can also be config-
ured as two receivers or two transmitters, permitting two
unidirectional streams into or out of the same SPORT. This bidi-
rectional functionality provides greater flexibility for serial
communications. Further, two SPORTs can be combined to enable
full-duplex, dual-stream communications.
• All serial data signals have programmable receive and transmit
functions and thus have one transmit and one receive data buffer
register (double buffer). There is also a bidirectional shift register
associated with each serial data signal. Double buffering provides
additional time to service the SPORT.
• A serial clock and frame sync provide signals in a wide range of fre-
quencies. Alternately, the SPORT can accept clock and frame sync
input from an external source, as described in Figure 5-10 on
page 5-70.
• The processors allow interrupt-driven, single word transfers to and
from on-chip memory controlled by the core, described in “Single
Word Transfers” on page 5-81.
• DMA transfers to and from on-chip memory. Each SPORT can
automatically receive or transmit an entire block of data. Further
the SPORTs on the processors offer chained DMA operations for
multiple data blocks, see “Chaining DMA Processes” on page 2-14.
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