ADSP-21368 SHARC Processor Hardware Reference 12-5
Two Wire Interface Controller
TWIDIV Register
During master mode operation, the serial clock divider register (TWIDIV)
values are used to create the high and low durations of the serial clock
(SCL). Serial clock frequencies can vary from 400 kHz to less than 20 kHz.
The resolution of the generated clock is 1/10 MHz or 100 ns.
CLKDIV = TWI SCL period ÷ 10 MHz time reference
For example, for an SCL of 400 kHz (period = 1/400 kHz = 2500 ns) and
an internal time reference of 10 MHz (period = 100 ns):
CLKDIV = 2500 ns ÷ 100 ns = 25
For an SCL with a 30% duty cycle, then CLKLOW = 17 and CLKHI = 8.
Note that CLKLOW and CLKHI add up to CLKDIV.
Additional information for the TWIDIV register bits can be found in “Clock
Divider Register (TWIDIV)” on page A-132.
Slave Mode Control Register
The TWI slave mode control register (TWISCTL) controls the logic associ-
ated with slave mode operation. Settings in this register do not affect
master mode operation and should not be modified to control master
mode functionality.
Additional information for the
TWISCTL register bits can be found in
“Slave Mode Control Register (TWISCTL)” on page A-133.
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