External Memory Interface
3-4 ADSP-21368 SHARC Processor Hardware Reference
wide external port. When executing from external asynchronous memory,
instruction throughput depends on the settings of asynchronous memory
such as the number of wait states, the ratio of core to peripheral clock and
other settings. For details, please refer to the external port global control
register (
EPCTL), asynchronous memory interface control register
(AMICTLx), and SDRAM control register (SDCTL) documentation in the
ADSP-2136x SHARC Processor Hardware Reference for the
ADSP-21367/8/9 Processors.
The SDRAM controller along with the processor core incorporates appro-
priate enhancements so that the code can be fetched from the SDRAM at
the maximum possible throughput. Throughput is limited only by
SDRAM when the code executes sequentially.
The address map for code is same as the data—each address refers to a
32-bit word. Any address produced by the sequencer is checked to deter-
mine if it falls in the external memory and if it does, the SDRAM
controller initiates access to the SDRAM. Because the sequencer address
bus is limited to 24 bits, only part of the external memory address area can
be used to store code. As explained in the following section, “Location of
Interrupt Vector Table (IVT)”, the address generated by the sequencer
undergoes translation to produce physical address, since the SDRAM data
bus width is less than 48 bits.
Location of Interrupt Vector Table (IVT)
On ADSP-2137x processors, the interrupt vector table always starts at the
top of internal memory at address 0x90000. This is set by programming
the IIVT bit in the system control register (SYSCTL). Therefore, if code exe-
cution from external memory is desired upon reset, the program needs to
set up the appropriate interrupt vector tables in internal memory as part of
the boot-up code before beginning to execute instructions from external
memory.
To Next Page
Loading...
Need help?
General
