ADSP-21368 SHARC Processor Hardware Reference 6-13
Serial Peripheral Interface Ports
immediately reconfigured as a slave. In order to safely transition from one
master to the other, the SPI port uses open drain outputs for the data pin
drivers. This helps to avoid possible damage from data contention.
More information on this topic is described in “Mode Fault Error
(MME)” on page 6-35.
SPI Data Transfer Operations
The following sections provide information on the two methods the pro-
cessors use to transfer data—through the core or through DMA.
SPI Operation Using the Core
For core-driven SPI transfers, the software must read from or write to the
RXSPIx and TXSPIx registers respectively to control the transfer. It is
important to check the buffer status before reading from or writing to
these registers because the core does not hang when it attempts to read
from an empty buffer or write to a full buffer. When the core writes to a
full buffer, the data that is in that buffer is overwritten and the SPI begins
transmitting the new data. Invalid data is obtained when the core reads
from an empty buffer.
For a master, when the transmit buffer becomes empty, or the receive
buffer becomes full, the SPI device stalls the SPI clock until all the data
from the receive buffer is read or it detects that the transmit buffer con-
tains a piece of data, depending upon the
TIMOD setting in the SPICTL
register.
• When a master is configured with TIMOD = 01 and the transmit
buffer becomes empty, the SPI device stalls the SPI clock until a
piece of data is written to the transmit buffer.
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