I/O Processor Registers
A-2 ADSP-21368 SHARC Processor Hardware Reference
• “Power Management Control Register (PMCTL)” on page A-170
• “Hardware Breakpoint Control Register” on page A-175
• “Enhanced Emulation Status Register” on page A-179
When writing programs, it is often necessary to set, clear, or test bits in
the processor’s registers. While these bit operations can all be done by
referring to the bit’s location within a register or (for some operations) the
register’s address with a hexadecimal number, it is much easier to use sym-
bols that correspond to the bit or register name. For convenience and
consistency, Analog Devices provides a header file that provides these bit
and registers definitions. An
#include file is provided with VisualDSP++
tools and can be found in the VisualDSP/2136x/include directory.
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Many registers have reserved bits. When writing to a register, pro-
grams may only clear (write zero) the register’s reserved bits.
I/O Processor Registers
The I/O processor’s registers are accessible as part of the processor’s mem-
ory map. These registers occupy addresses 0x0000 0000 through 0x0003
FFFF of the memory map. The I/O registers control the following DMA
operations: serial port, serial peripheral interface port (SPI), and input
data port (IDP), and internal memory-to-memory transfers.
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I/O processor registers have a one cycle effect latency (changes take
effect on the second cycle after the change).
Since the I/O processor’s registers are part of the processor’s memory map,
buses access these registers as locations in memory. While these registers
act as memory-mapped locations, they are separate from the processor’s
internal memory and have different bus access. One bus can access one
I/O processor register from one I/O processor register group at a time.
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