Analog Devices SHARC ADSP-21368 User Manual

SDRAM Controller
3-78 ADSP-21368 SHARC Processor Hardware Reference
The workaround is to break up this instruction into separate
instructions and use the workaround similar to case #1.
r0=dm(IOP);
NOP;
r8=pm(Ext_Mem);
External Memory Access Restrictions
The following restrictions should be noted when writing programs for the
ADSP-21367/8/9 and ADSP-2137x processors.
1. The processor does not execute from external memory in SIMD
mode and the LW mnemonic is not applicable to external memory.
2. In a dual-data move instruction, both accesses should not be to
external memory.
3. Conditional accesses to external memory should not be based on
any of the FLAG pin status.
4. If there is an aborted or interrupted conditional read to an external
memory, the processor generates a spurious read. This is an issue
for FIFO devices and not standard memories.
5. Any sequence of IOP register access (read or write) followed by an
external memory read, causes incorrect data to be read from exter-
nal memory. To workaround this restriction, separate the IOP and
external memory access by adding a NOP instruction or any other
instruction which is not either an IOP read/write, or an external
memory read.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP