Analog Devices SHARC ADSP-21368 User Manual

ADSP-21368 SHARC Processor Hardware Reference 2-3
I/O Processor
• Serial peripheral interface ports (SPI)
• Input data port (IDP)
4. Enable DMA
• Set the applicable bits in the appropriate control registers
For peripheral specific DMA information, see the following sections.
• “External Port DMA” on page 2-35
• “Serial Port DMA” on page 2-40
• “Serial Peripheral Interface DMA” on page 2-42
• “UART DMA” on page 2-44
• “Memory-to-Memory DMA” on page 2-48
Core Access to IOP Registers
In certain cases, extra core cycles are needed to process register accesses.
The access cycles are shown in Table 2-1 and the registers are shown in
Table 2-2.
Table 2-1. I/O Processor Stall Conditions
Type Of Access Number of Core Cycles
Core write
1
1
Core read
1
2
Unconditional, isolated I/O processor register
write
2
1
Unconditional I/O processor register write after a
write
2
2 (back-to-back)
Unconditional I/O processor register read
2
7/8

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP