Pulse Width Modulation Registers
A-84 ADSP-21368 SHARC Processor Hardware Reference
PWM Channel Duty Control Registers
(PWMAx, PWMBx)
The duty cycle control registers, described in Table A-30, directly control
the duty cycles of the two pairs of PWM signals. These 16-bit, read/write
registers are located at addresses:
PWM Channel Low Duty Control Registers
(PWMALx, PWMBLx)
In non-paired mode, these registers, described in Table A-31 are used to
program the low side duty cycle. These can be different then the high-side
cycles. These 16-bit read/write registers are located at addresses:
PWMA0 — 0x3005 PWMB0 — 0x3006
PWMA1 — 0x3015 PWMB1 — 0x3016
PWMA2 — 0x3405 PWMB2 — 0x3406
PWMA3 — 0x3415 PWMB3 — 0x3416
Table A-30. PWMAx/PWMBx Register Bit Descriptions
Bit Name Description
15–0 PWMAx Channel A Duty Cycle. Program a two’s complement
duty cycle with a value of 0x0000 through 0xFFFF.
Default = 0
15–0 PWMBx Channel B Duty Cycle. Program a two’s complement
duty cycle with a value of 0x0000 through 0xFFFF.
Default = 0
PWMAL0 — 0x300A PWMBL0 — 0x300B
PWMAL1 — 0x301A PWMBL1 — 0x301B
PWMAL2 — 0x340A PWMBL2 — 0x340B
PWMAL3 — 0x341A PWMBL3 — 0x341B
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