ADSP-21368 SHARC Processor Hardware Reference 1-11
Introduction
Differences From Previous Processors
This section identifies differences between the ADSP-21367/8/9 and
ADSP-2137x processors and previous SHARC processors: ADSP-21161,
ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and
ADSP-21065L. Like the ADSP-2116x family, the ADSP-2136x SHARC
processor family is based on the original ADSP-2106x SHARC family.
The ADSP-21367/8/9 and ADSP-2137x processors preserve much of the
ADSP-2106x architecture and is code compatible to the ADSP-21160,
while extending performance and functionality. For background informa-
tion on SHARC processors and the ADSP-2106x family DSPs, see the
ADSP-2106x SHARC User’s Manual or the ADSP-21065L SHARC DSP
Technical Reference.
I/O Architecture Enhancements
The I/O processor provides much greater throughput than that on the
ADSP-2106x processors.
The DMA controller supports up to 34 channels compared to 14 channels
on the ADSP-21161 processor. DMA transfers occur at clock speed in
parallel with full speed processor execution. The ADSP-21367/8/9 and
ADSP-2137x processors also provide delay line DMA functionality. This
allows processor reads and writes to external delay line buffers (and hence
to external memory) with limited core interaction.
In addition to the above, the ADSP-21367/8/9 and ADSP-2137x proces-
sors have up to eight serial ports (SPORTs), a 32-bit external memory
interface, a universal asynchronous transmitter/receiver (UART) and an
I
2
C compatible interface called the TWI (two wire interface).
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