ADSP-21368 SHARC Processor Hardware Reference 3-1
3 EXTERNAL PORT
The external ports of the ADSP-21367/8/9 and ADSP-2137x processors
are comprised of the following modules.
•An “Asynchronous Memory Interface” on page 3-20 which com-
municates with SRAM, FLASH, and other devices that meet the
standard asynchronous SRAM access protocol. The AMI supports
16M words of external memory in bank1, bank2, and bank3 and
14M words of external memory in bank0. The maximum external
data is 64M bytes on bank1.
Each bank is individually programmed to access a single memory,
either SDRAM or asynchronous.
• An SDRAM controller that supports a glueless interface with any
of the standard SDRAMs of 32, 64, 128, 256, and 512M bit. See
“SDRAM Controller” on page 3-30.
•A “Shared Memory Interface” on page 3-79 that allows the connec-
tion of up to four ADSP-21368 processors to create shared external
bus systems (ADSP-21368 only).
• A DMA interface between internal and external memory that
directs processor core accesses to external memory locations. For
more information, see Chapter 2, I/O Processor.
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