Analog Devices SHARC ADSP-21368 User Manual

Data Delays, Latencies, and Throughput
14-54 ADSP-21368 SHARC Processor Hardware Reference
Instruction 3: Instruction involving post-modify addressing involv-
ing same
I register such as R0 = DM(I1,M2);. This last instruction
stalls the processor for one cycle.
• Any read reference to a memory-mapped register located physically
within the core (registers like SYSCTL, which are not situated in the
IOP) requires two cycles; therefore, the processor stalls for one
cycle.
• Any read reference to a memory-mapped register located within a
peripheral such as the SPI, SPORTS, or IDP requires a minimum
of four cycles; so the minimum stall is three cycles.
• Any reference to a memory-mapped register in a conditional
instruction stalls the processor for one extra cycle (with respect to
an unconditional instruction).
• Writes to program memory breakpoint address registers (PMDAS,
PMDAE) have an effect latency of one cycle. Therefore, the break-
point address ranges are effective one cycle after the breakpoint
address registers are initialized.
DAG Stalls
One cycle hold on register conflict. For more information on DAG opera-
tions, see the ADSP-2136x SHARC Processor Programming Reference.
Memory Stalls
One cycle on PM and DM bus access to the same block of internal
memory.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP