ADSP-21368 SHARC Processor Hardware Reference 12-19
Two Wire Interface Controller
4. Program the
TWIMCTL register. Ultimately this prepares and enables
master mode operation. As an example, programming the value
0x0201 enables master mode operation, generates a 7-bit address,
sets the direction to master-receive, uses standard mode timing,
and receives 8 data bytes before generating a stop condition.
Table 12-4 shows what the interaction between the TWI controller and
the processor might look like using this example.
Repeated Start Condition
In general, a repeated start condition is the absence of a stop condition
between two transfers initiated by the same master. The two transfers can
be of any direction type. Examples include a transmit followed by a
receive, or a receive followed by a transmit. During a repeated start trans-
fer, each interrupt must be serviced correctly to avoid errors. The
following sections are intended to assist the programmer with service rou-
tine development.
Transmit/Receive Repeated Start Sequence
Figure 12-8 illustrates a repeated start data transmit followed by a data
receive sequence.
Table 12-4. Master Mode Receive Setup Interaction
TWI Controller Master Processor
Interrupt: TWIRXINT – Receive buffer has 1
or 2 bytes (according to RCVINTLEN).
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
... ...
Interrupt: TWIMCOMP – Master transfer
complete.
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
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