SDRAM Controller
3-60 ADSP-21368 SHARC Processor Hardware Reference
Single Bank Operation
The SDC keeps only one page open at a time, however, driving four exter-
nal memory selects populated with SDRAM, the effective page size is
increased up to four pages.
Multibank Operation (ADSP-2137x Processors)
Since an SDRAM contains four independent internal banks (A–D), the
SDC on the ADSP-2137x processors is capable of supporting multibank
operation, thus taking advantage of the architecture.
Any first access to SDRAM bank (A) forces an activate command before a
read or write command. However, if any new access falls into the address
space of the other banks (B, C, or D) the SDC leaves bank (A) open and
activates any of the other banks (B, C, or D). Bank (A) to bank (B) active
time is controlled by t
RRD
= t
RCD
+ 1. This scenario is repeated until all
four banks (A–D) are opened and results in an effective page size of up to
four pages. This is because the absence of latency allows switching
between these open pages (as compared to one page in only one bank at a
time). Any access to any closed page in any opened bank (A–D) forces a
precharge command only to that bank. If, for example, two external port
DMA channels are pointing to the same internal SDRAM bank, this
always forces precharge and activation cycles to switch between the differ-
ent pages. However, if the two external port DMA channels are pointing
to different internal SDRAM banks, there is no additional overhead. See
Figure 3-9.
Furthermore the SDC supports four external memory selects containing
each SDRAM. However only the MS0 and MS1 signals provide multibank
support, so the maximum number of open pages is 2 × 4 + 2 × 1 = 10
pages.
L
Multibank operation reduces precharge and activation cycles by
mapping opcode/data among different internal SDRAM banks
driven by the A[18:17] pins and external memory selects (MSx).
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