ADSP-21368 SHARC Processor Hardware Reference 7-25
Input Data Port
DMA Transfer Notes
The following items provide general information about DMA transfers.
• A DMA can be interrupted by changing the
IDP_DMA_EN bit in the
IDP_CTL0 register. None of the other control settings (except for
the IDP_ENABLE bit) should be changed. Clearing the IDP_DMA_EN
bit (= 0) does not affect the data in the FIFO, it only stops DMA
transfers. If the IDP remains enabled, an interrupted DMA can be
resumed by setting the IDP_DMA_EN bit again. But resetting the
IDP_ENABLE bit flushes the data in the FIFO. If the bit is set again,
FIFO starts accepting new data.
• Using DMA transfers overrides the mechanism that is used for
interrupt-driven manual reads from the FIFO. When the
IDP_DMA_EN bit and at least one IDP_DMA_ENx bit in the IDP_CTL1
register are set, the eighth interrupt in the DAI_IRPTL_L or
DAI_IRPTL_H registers (IDP_FIFO_GTN_INT) is not generated. This
interrupt detects the condition that the number of data available in
FIFO is more than the number set in the IDP_NSET bits (bits 3–0 of
the IDP_CTL0 register).
• At the end of the DMA transfer for individual channels, interrupts
are generated. These interrupts are generated after the last DMA
data from a particular channel has been transferred to memory.
These interrupts are mapped to the
IDP_DMA7_INT bit (bit 17), and
to the
IDP_DMA0_INT bit (bit 10) in the DAI_IRPTL_L or
DAI_IRPTL_H registers and they generate interrupts when they are
set (= 1). These bits are ORed and reflected in high-level interrupts
sent to the core.
• If the combined data rate from the channels is more than the DMA
can service, a FIFO overflow occurs. This condition is reflected for
each channel by the individual overflow bits (SRU_OVF) in the
DAI_STAT register. These are W1C bits that must be cleared by
writing to the
IDP_CLROVR bit (bit 6 of the IDP_CTL0 register).
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