FIFO to Memory Data Transfer
7-24 ADSP-21368 SHARC Processor Hardware Reference
•
IDP_Pxx_PDAPMASK bits in the IDP_PP_CTL register to specify
the input mask, if the PDAP is used. For more information,
see “Parallel Data Acquisition Port Control Register
(IDP_PP_CTL)” on page A-74.
• IDP_PORT_SELECT bits in the IDP_PP_CTL register to specify
input from the DAI pins or the data pins, if the PDAP is
used.
• IDP_PDAP_CLKEDGE bit (bit 29) in the IDP_PP_CTL register to
specify if data is latched on the rising or falling clock edge, if
the PDAP is used.
5. Connect all of the inputs to the IDP by writing to the SRU_DAT4
and SRU_DAT5, SRU_FS2 and SRU_FS3, SRU_CLK2 and SRU_CLK3 regis-
ters. Keep the clock and frame sync of the ports connected to low
when data transfer is not intended.
6. Enable DMA, IDP, and PDAP (if required) by setting each of the
following bits = 1:
• IDP_DMA_EN bit (bit 5 of the IDP_CTL0 register)
• IDP_PINGx bit in IDP_CTL1 register to enable the ping-pong
DMA of the selected channel
• IDP_PDAP_EN bit (bit 31 in IDP_PP_CTL register)
•
IDP_ENx of IDP_CTL1 to enable the selected channel
• IDP_ENABLE bit (bit 7 in the IDP_CTL0 register)
7. After the DMA completes, connect the clock and frame sync sig-
nals to 0.
L
An interrupt is generated after every ping and pong DMA transfer
(when the count = 0).
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