ADSP-21368 SHARC Processor Hardware Reference 7-23
Input Data Port
Starting Ping-Pong DMA Transfers
To start a ping-pong DMA transfer from the FIFO to memory:
1. Clear and halt the FIFO by setting (= 1) and then clearing (= 0) the
IDP_ENABLE bit (bit 7 in the IDP_CTL0 register).
2. While the IDP_DMA_EN and IDP_ENABLE bits are low, set the values
for the following DMA parameter registers that correspond to
channels 7–0. If some channels are not going to be used, then the
corresponding parameter registers can be left in their default states:
• First index registers IDP_DMA_AIx
• Second index registers IDP_DMA_BIx
• Modifier register IDP_DMA_Mx
• Counter register IDP_DMA_PCx. For each of these registers x
is 0–7 which corresponds to channels 0 to 7. See “IDP
Ping-Pong Count Registers (IDP_DMA_PCx)” on
page A-73.
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to low, by setting proper values in the
SRU_CLK2 and SRU_CLK3 as well as the SRU_FS2 and SRU_FS3 regis-
ters. For more information, see “DAI/SRU1 Connection Groups”
on page 4-18.
4. Set the required values for:
•
IDP_SMODEx bits in the IDP_CTL0 register to specify the frame
sync format for the serial inputs (I
2
S, left-justified sample
pair, or right-justified sample pair modes).
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