ADSP-21368 SHARC Processor Hardware Reference 3-39
External Port
For more information on SDRAM clocking and programming the PLL,
see “Clock Derivation” on page 14-13, “Power Management Control Reg-
ister” on page 14-14, and “Power Management Control Register
(PMCTL)” on page A-170.
Parallel Connection of SDRAMs
To specify a SDRAM system, multiple possibilities are given based on the
different memory sizes. For a 32-bit I/0 capability, the following can
configured.
• 1 x 32-bit/page 256 words
• 2 x 16-bit/page 512 words
• 4 x 8-bit/page 1k words
• 8 x 4-bit/page 2k words
The SDRAM’s page size is used to determine the system you select. All
four systems have the same external bank size, but different page sizes.
Note that larger page sizes, allow higher performance but larger page sizes
require more complex hardware layouts.
L
Even if connecting SDRAMs in parallel, the SDC always considers
the cluster as one external SDRAM bank because all address and
control lines feed the parallel parts.
SDRAM Control Register (SDCTL)
The SDRAM memory control register includes all programmable parame-
ters associated with the SDRAM access timing and configuration. These
bits are described below. For more information, see “SDRAM Control
Register (SDCTL)” on page A-21.
To Next Page
Loading...
Need help?
General
