Analog Devices SHARC ADSP-21368

Pulse Width Modulation Registers
A-82 ADSP-21368 SHARC Processor Hardware Reference
PWM Output Disable Registers (PWMSEGx)
These 16-bit read/write registers, described in Table A-28, control the
output signals of the four PWM groups. The addresses for these registers
are:
PWMSEG0 — 0x3008
PWMSEG1 — 0x3018
PWMSEG2 — 0x3408
PWMSEG3 — 0x3418
Table A-28. PWMSEGx Register Bit Descriptions
Bit Name Description
0 PWM_BH Channel B High Disable. Enables or disables the channel B
output signal.
0 = Enable
1 = Disable
1 PWM_BL Channel B Low Disable. Enables or disables the channel B out-
put signal.
0 = Enable
1 = Disable
2 PWM_AH Channel A High Disable. Enables or disables the channel A
output signal.
0 = Enable
1 = Disable
3 PWM_AL Channel A Low Disable. Enables or disables the channel A
output signal.
0 = Enable
1 = Disable